Multi-mode forward error correction

ABSTRACT

According to one embodiment, a system for multi-mode forward error correction comprises a substrate, forward error correction (FEC) modules, and a controller. The FEC modules are disposed outwardly from the substrate. A first FEC module performs forward error correction according to a first FEC scheme, and a second FEC module performs forward error correction according to a second FEC scheme. The controller configures the first FEC module and the second FEC module to convert from an input FEC scheme to an output FEC scheme for a stream.

RELATED APPLICATION

This application claims benefit under 35 U.S.C. §119(e) of U.S.Provisional Application Ser. No. 61/102,046, entitled “Multi-ModeForward Error Correction Support for Optical Nodes,” filed Oct. 2, 2008.

TECHNICAL FIELD

This invention relates generally to the field of communication systemsand more specifically to multi-mode forward error correction.

BACKGROUND

Optical signal noise in optical transport networks can create problems.For example, such noise can limit the maximum span length and/or numberof spans of the network. Such noise can also restrict the number ofchannels in a dense wavelength division multiplexing (DWDM) system andcan limit the number of transparent optical network elements between 3Rregeneration. Furthermore, optical signal noise requires tight componentparameters.

Forward error correction (FEC) can counteract the effects of opticalnoise. Forward error correction includes Reed Solomon FEC (RSFEC),Enhanced FEC (EFEC) (such as EFEC provided by APPLIED MICRO CIRCUITSCORPORATION), and Ultra FEC (UFEC) (such as UFEC provided by CORTINASYSTEMS).

SUMMARY OF THE DISCLOSURE

In accordance with the present invention, disadvantages and problemsassociated with previous techniques for forward error correction may bereduced or eliminated.

According to one embodiment, a system for multi-mode forward errorcorrection comprises a substrate, forward error correction (FEC)modules, and a controller. The FEC modules are disposed outwardly fromthe substrate. A first FEC module performs forward error correctionaccording to a first FEC scheme, and a second FEC module performsforward error correction according to a second FEC scheme. Thecontroller configures the first FEC module and the second FEC module toconvert from an input FEC scheme to an output FEC scheme for a stream.

Certain embodiments of the invention may provide one or more technicaladvantages. A technical advantage of one embodiment may be that a systemincludes a first FEC module that performs forward error correctionaccording to a first FEC scheme and a second FEC module that performsforward error correction according to a second FEC scheme. The FECmodules may also perform forward error correction according to a commonFEC scheme. The FEC modules may provide multiple FEC schemes as well asconversion among the FEC schemes. Another technical advantage of oneembodiment may be that the system may include clocking subsystems thatprovide clock signals that allow the apparatus to accommodate differenttypes and rates of signals.

Certain embodiments of the invention may include none, some, or all ofthe above technical advantages. One or more other technical advantagesmay be readily apparent to one skilled in the art from the figures,descriptions, and claims included herein.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and itsfeatures and advantages, reference is now made to the followingdescription, taken in conjunction with the accompanying drawings, inwhich:

FIG. 1 illustrates one embodiment of a system that provides forwarderror correction for an optical network;

FIG. 2 illustrates an example of the system of FIG. 1;

FIG. 3 illustrates examples of a UFEC module and an EFEC module that maybe used with the system of FIG. 1;

FIGS. 4 through 7 illustrate examples of methods that may be used forunidirectional 3R regeneration;

FIGS. 8 through 10 illustrate examples of methods that may be used forOptical channel Transport Unit (OTU) conversion;

FIGS. 11 and 12 illustrate examples of methods that may be used forconversion between OTU Optical Carrier 192 (OC192)/10 GigabitEthernet-wide area network (10GE-WAN) signals;

FIGS. 13 and 14 illustrate examples of methods that may be used forconversion between OTU Optical Carrier 192 (OC192) and 10 GigabitEthernet/10 Gigabit Fiber Channel (10GFC) Overclocked; and

FIGS. 15 and 16 illustrate examples of methods that may be used forconversion between OTU and Optical Carrier 192 (OC192) 10 GigabitEthernet Generic Framing Procedure-Frame Mode(GFP-F)/GFP-Semi-Transparent (GFP-ST).

DETAILED DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention and its advantages are bestunderstood by referring to FIGS. 1 through 16 of the drawings, likenumerals being used for like and corresponding parts of the variousdrawings.

FIG. 1 illustrates one embodiment of a system 10 that provides forwarderror correction for a network that communicates information usingsignals. In certain embodiments, system 10 includes a first FEC modulethat performs forward error correction according to a first FEC schemeand a second FEC module that performs forward error correction accordingto a second FEC scheme. The FEC modules may also perform forward errorcorrection according to a common FEC scheme. The FEC modules may providemultiple FEC schemes as well as conversion among the FEC schemes.

In certain embodiments, system 10 includes a network interface 20, aUFEC module 24, an EFEC module 26, a client interface 32, a clockingsystem 38, and a controller 40 coupled as shown. Network interface 20interfaces with a receive path 33 and a transmit path 34 coupled tonetwork-side elements. Client interface 32 interfaces with a receivepath 36 and a transmit path 35 coupled to client-side devices.

Forward error correction (FEC) modules 24 and 26 perform forward errorcorrection, and may comprise any device suitable to be configured toperform forward error correction, such as application specific standardproduct (ASSP) integrated circuits (ICs).

In certain embodiments, FEC module 24 may support a first FEC scheme,and FEC module 26 may support a second FEC scheme that is not compatiblewith the first FEC scheme. Both FEC modules 24 and 26 may support acommon FEC scheme.

The first, second, and common FEC schemes may be any suitable FECschemes. For example, each FEC scheme may be selected from any suitableReed Solomon FEC (RSFEC), Enhanced FEC (EFEC), and/or Ultra FEC (UFEC)schemes. An example of an EFEC scheme may be the EFEC scheme describedby the G.975.1 I.4 standard, and of a UFEC scheme may be the UFEC schemedescribed by the G.975.1 I.7 standard. In the illustrated embodiment,UFEC module 24 supports UFEC and RSFEC schemes, and EFEC module 26supports EFEC and RSFEC schemes. Modules 24 and 26, however, may supportany suitable FEC schemes.

Clocking system 38 generates clock frequencies and clock traceabilitiesappropriate for particular input and/or output signals. In certainembodiments, clocking system 38 includes discrete phase lock loops(PLLs) and programmable clock synthesizers.

Controller 40 controls the operations of system 10. In certainembodiments, controller 40 identifies an input FEC scheme of a streamand an output FEC scheme of the stream, and configures FEC modules 24and 26 perform a conversion from the input FEC scheme to the output FECscheme. In certain embodiments, controller 40 identifies an input signaltype of a stream and an output signal type of the stream, and configuresclocking system 38 to perform a conversion from the input signal type tothe output signal type.

As an example, controller 40 identifies that an input FEC scheme is theUFEC scheme and that an output FEC scheme is also the UFEC scheme.Controller 40 may then configure UFEC module 24 to perform forward errorcorrection according to the UFEC scheme.

As another example, controller 40 identifies that an input FEC scheme isthe EFEC scheme and that an output FEC scheme is also the EFEC scheme.Controller 40 may then configure EFEC module 26 to perform forward errorcorrection according to the EFEC scheme.

As another example, controller 40 identifies that an input FEC scheme isthe UFEC scheme and that an output FEC scheme is the EFEC scheme.Controller 40 may then configure UFEC module 24 to perform forward errorcorrection according to the UFEC scheme and EFEC module 26 to performforward error correction according to the EFEC scheme. The interfacebetween FEC modules 26 and 28 may perform RSFEC or no FEC.

The examples illustrate a transponder type application, but embodimentsmay be used in any suitable application. For example, embodiments may beused in an application that is connected to a backplane, such as that ofa switch fabric. In these embodiments, client interface 32 may bereplaced with the backplane or switch fabric.

Controller 40 and other components of system 10 are described in moredetail with reference to the following figures. A component of system 10may include an interface, logic, memory, and/or other suitable elements.An interface receives input, sends output, processes the input and/oroutput, and/or performs other suitable operation. An interface maycomprise hardware and/or software.

Logic performs the operations of the component, for example, executesinstructions to generate output from input. Logic may include hardware,software, and/or other logic. Logic may be encoded in one or moretangible media and may perform operations when executed by a computer.Certain logic, such as a processor, may manage the operation of acomponent. Examples of a processor include one or more microprocessors,one or more applications, and/or other logic.

In particular embodiments, the operations of the embodiments may beperformed by one or more computer readable media encoded with a computerprogram, software, computer executable instructions, and/or instructionscapable of being executed by a computer. In particular embodiments, theoperations of the embodiments may be performed by one or more computerreadable media storing, embodied with, and/or encoded with a computerprogram and/or having a stored and/or an encoded computer program.

A memory stores information. A memory may comprise one or more tangible,computer-readable, and/or computer-executable storage medium. Examplesof memory include computer memory (for example, Random Access Memory(RAM) or Read Only Memory (ROM)), mass storage media (for example, ahard disk), removable storage media (for example, a Compact Disk (CD) ora Digital Video Disk (DVD)), database and/or network storage (forexample, a server), and/or other computer-readable medium.

FIG. 2 illustrates an example of system 10 of FIG. 1. In certainembodiments, system 10 includes network interface 20, UFEC module 24,EFEC module 26, client interface 32, and clocking system 38 (38 a,and/or 38 d) coupled as shown.

In certain embodiments, network interface 20 comprises a variableoptical attenuator (VOA), a narrow band optical module (NBO), and/or aMulti-Source Agreement (MSA) transceiver circuit. The variable opticalattenuator reduces the incoming signal level to the range of the narrowband optical module. The narrow band optical module performs receive(Rx) clock data recovery (CDR) and transmit and/or receive (Tx/Rx)Serializer/Deserializer (SerDes) operations.

In certain embodiments, client interface 32 comprises a 10 Gigabit(Gbit) small form factor pluggable (XFP) and a transceiver circuit. Thesmall form factor pluggable performs electrical-to-optical and/oroptical-to-electrical conversion. The transceiver circuit performsreceive (Rx) clock data recovery (CDR) and transmit and/or receive(Tx/Rx) Serializer/Deserializer (SerDes) operations.

UFEC module 24 may comprise any suitable processor, for example, theTENABO IXF30011 Optical Transport Processor. In certain embodiments,UFEC module 24 may be configured as a SONET framer providing section andline termination for Optical Carrier192 (OC192) signals. UFEC module 24may be operated as a bridge device to transport frames over a G.709compliant network. UFEC module 24 may have system and/or line interfacesequipped with a G.709 compliant FEC codec (RS-255,239) and/or SFI-4compliant interfaces.

EFEC module 26 may comprise any suitable processor, for example, theRUBICON (S19227) provided by APPLIED MICRO CIRCUITS CORPORATION. Incertain embodiments, EFEC module 26 may provide Enhanced gain ForwardError Correction (EFEC) with ODU-2. EFEC module 26 may perform othersuitable operations, such as ingress and egress client performancemonitoring, client and line loop back functions, LAN transport throughan OTN network, and/or G.709 ODU-2 synchronous and asynchronous mappingwith G.709 overhead processing.

In certain embodiments, clocking system 30 includes discrete phase lockloops (PLLs) and programmable clock synthesizers that generate thedesired frequencies and clock traceabilities. The phase lock loops mayinclude one or more system PLLs SYS-PLLs 42 a and 42 b and one or moreasynchronous PLLs ASYNC-PLLs 42 c. System PLLs 42 a and 42 b reference abackplane clock to create a system traceable reference clock sys-60 mfor use by the data path clock synthesizers of system 38. Referenceclock may have any suitable reference clock frequency. In theillustrated example, the reference clock frequency is 60.75 MHz.Asynchronous PLL 42 c creates a smooth clock async-60 m traceable to aclient signal extracted from the network side. The asynchronous PLL canbe configured to lock to reference/feedback signals from modules 24 or26.

The clock synthesizers may include a network line clock synthesizerCSYN-NL 44 a, a client line clock synthesizer CSYN-CL 44 b, traceablereference clock synthesizers CSYN-DP1 46 a and CSYN-DP4 46 b, outputclock synthesizers CSYN-DP2 48 a, DP3 48 b, DP5 48 c, and DP6 48 d.

Network line clock synthesizer 44 a translates a recovered clock fromnetwork interface 20 to the reference clock frequency to yield referencen1-60 m that serves as an available reference for other clocksynthesizers (for example, DP2, DP3, DP5, DP6) that may be slave to thenetwork line. Client line clock synthesizer 44 b translates a recoveredclock from client interface 36 to the reference clock frequency to yieldreference c1-60 m that serves as an available reference for other clocksynthesizers that may be slave to the client line. Different programmingfiles may be loaded into the synthesizers to account for differentrecovered clock frequencies. The programming files may be loaded basedon application/port mode.

Traceable reference clock synthesizers CSYN-DP1 46 a and CSYN-DP4 46 bmultiply the reference clock to yield system traceable references. Thereferences may be used by the CDR operations of network interface 20 andclient interface 36, respectively. Different programming files may beloaded into the synthesizers to account for different reference clockfrequencies of the network and client ports. The programming files maybe loaded based on application.

Reference selectors 47 (47 a, . . . , 47 d) select a reference, and maycomprise software that enables the hardware to switch references.References may be switched in any suitable situation, for example, inresponse to detecting defects. Output clock synthesizers CSYN-DP2 48 a,DP3 48 b, DP5 48 c, and DP6 48 d generate the output clocks for theclient side of module 24, client side of module 26, network side ofmodule 26, and network side of module 24, respectively. Each synthesizercan be independently configured by software to reference any suitablereference, such as sys-60 m, n1-60 m, n1-60M, or async-60 m. In certainembodiments, a selector 50 selects either network or client referenceclocks as reference clock.

In certain embodiments, controller 40 configures the clocking system 38according to several factors, which may include client and networkrates, mapping/application mode, FEC support, presence of provisionedloop backs, port TCLK timing provisioning (Thru, System, Loop), or othersuitable factor.

Controller 40 may perform any suitable operation for configured clockingsystem 38. Controller 40 may download configuration files. For example,controller 40 may download configuration files for clock synthesizers(CSYN-NL, CSYN-CL, CSYN-DP1 thru DP6) to produce the desired clockfrequencies. In addition, controller 40 may select reference clocksand/or reference clock sources. For example, controller 40 may selectthe reference clock CSYN-DP2, DP3, DP5, or DP6 to attain appropriatetiming traceability or may select modules 24 or 26 as thereference/feedback clock sources for the Async-PLL. In addition,controller 40 may configure the auto reference switching (ARS) logic.For example, controller 40 may enable/disable the ARS for CSYN-DP2 DP3,DP5, or DP6, or select the ARS clock qualification criteria forswitching away from the n1-60 m, c1-60 m, and async-60 m references.

FIG. 3 illustrates examples of UFEC module 24 and EFEC module 26 thatmay be used with system 10 of FIG. 1. In the illustrated embodiment,UFEC module 24 and EFEC module 26 are coupled to network interface 20,client interface 32, and an overhead processor 70 as shown.

In certain embodiments, UFEC module 24 includes a side A 80 a, a crossconnect 82, and a side B 80 b coupled as shown. Side A 80 a performsUFEC or RSFEC, and side B 80 b performs RSFEC. Each side 80 a and 80 bincludes a receive portion 84 a and 84 b, respectively, and a transmitportion 86 a and 86 b, respectively. Receive portion 84 a or 84 bperforms operations (such as FEC operations) for received packets, andtransmit portion 86 a or 86 b performs operations (such as FECoperations) for packets to be transmitted.

In certain embodiments, EFEC module 26 includes a line side 90 a andclient side 90 b coupled as shown. Line (LI) side 90 a performs EFEC,and client (CL) side 90 b performs RSFEC. Each side 90 a and 90 bincludes a receive portion 94 a and 94 b, respectively, and a transmitportion 96 a and 96 b, respectively. Receive portion 94 a or 94 bperforms operations (such as FEC operations) for received packets, andtransmit portion 96 a or 96 b performs operations (such as FECoperations) for packets to be transmitted.

In certain embodiments, overhead processor 70 generates overhead bytesas appropriate for UFEC module 24 and EFEC module 26.

FIGS. 4 through 16 illustrate examples of methods for handling FECschemes that may be used by system 10 of FIGS. 1 and 2 and modules 24and 26 of FIG. 3. The methods describe a FEC scheme X (such as the inputFEC scheme of a stream) and a FEC scheme Y (such as the output FECscheme of the stream). The methods may be performed in a reverse ordersuch that FEC scheme Y is the input FEC scheme and FEC scheme X is theoutput FEC scheme. In some cases, FEC scheme Y may be the same as FECscheme X. In other cases, FEC scheme Y may be different from FEC schemeX. In both types of cases, FEC scheme X may be regarded as “convertedto” FEC scheme Y. In the examples, “conversion between FEC scheme X andFEC scheme Y” may be expressed as “X

Y.”

The methods may be used for first signals (which may be receivedsignals) of a signal type J and second signals (which may be transmittedsignals) of a signal type K, which may the same as or different fromtype J. “Conversion between signal type J and signal type K” may beexpressed as “J

K.”

In certain embodiments, controller 40 receives information aboutdetected defects and/or received overhead from module 24 or 26 thatprocesses the stream.

FIGS. 4 through 7 illustrate examples of methods that may be used forunidirectional 3R regeneration. In the examples, a stream enters fromthe network side, FEC is performed, and the stream exits back to thenetwork side.

FIG. 4 illustrates an example of a method in which FEC scheme X is UFECor RSFEC and FEC scheme Y is UFEC or RSFEC, yielding UFEC

UFEC, RSFEC

RSFEC, UFEC

RSFEC, or RSFEC

UFEC. In the example, side A 80 a of UFEC module 24 performs theoperations. The stream travels through side A receive portion 84 a,cross connect 82, and side A transmit portion 86 a. At side A transmitportion 86 a, overhead processor 70 generates overhead bytes associatedwith the Session Management (SM) layer and any Tandem ConnectionMonitoring (TCM) layers provisioned for termination. Overhead bytesassociated with unterminated TCM layers and the Performance Management(PM) layer pass through unmodified. FEC (RSFEC or UFEC) is performed,and the stream is transmitted to network interface 20.

FIG. 5 illustrates an example of a method in which FEC scheme X is UFECor RSFEC and FEC scheme Y is EFEC, yielding UFEC

EFEC or RSFEC

EFEC. In the example, side A receive portion 84 a of UFEC module 24performs receive processing, and side B 80 b of UFEC module 24 generatesthe forward overhead bytes and RSFEC parity. EFEC module 26 hairpins thestream, aligns the stream to the incoming Frame Alignment Signal (FAS),and reencodes the stream to EFEC format. The stream is then transmittedback through UFEC module 24 to network interface 20.

FIG. 6 illustrates an example of a method in which FEC scheme X is EFECand FEC scheme Y is UFEC or RSFEC, yielding EFEC

RSFEC or EFEC

UFEC. In the example, UFEC module 24 is configured as a wire in path 33,which may allow EFEC module 26 to perform data alignment, overheadtermination, and/or EFEC decoding and/or correction operations. Thestream is hair pinned in EFEC module 26 using device internal loopbacks.

The stream then enters egress processing in the LI side transmit portion96 a of EFEC module 26. Overhead bytes associated with the SM layer andany TCM layers provisioned for termination are generated. Overhead bytesassociated with unterminated TCM layers and the PM layer pass throughunmodified. The stream is then RSFEC encoded and passed to UFEC module24. UFEC module 24 is configured to slave to the alignment of the streamand to regenerate the FEC parity bytes either using UFEC or RSFEC priorto sending the stream.

FIG. 7 illustrates an example of a method in which FEC scheme X is EFECand FEC scheme Y is EFEC, such as EFEC

EFEC. In the example, the network receive path may be similar to thatfor the EFEC

RS or UFEC method. For transmission to network interface 20, EFEC module26 is configured to generate EFEC parity, and UFEC module 24 for path 34is configured as a wire to transparently pass the output stream tonetwork interface 20 without modification.

FIGS. 8 through 10 illustrate examples of methods that may be used forOptical channel Transport Unit (OTU) conversion, that is, OTU

OTU, where OTU may be any suitable rate, such as OTU1, OTU2, or OTU3. Inthe examples, a stream enters from the network side, FEC is performed,and the stream exits to the client side, or vice-versa. In certainembodiments, SM layer termination may be implemented, and layers of TCMmay be provisioned for termination or as transparent pass-through.Overhead processing, including backward and forward defect generation,may be supported for terminated layers.

FIG. 8 illustrates an example of a method in which FEC scheme X is UFECor RSFEC and FEC scheme Y is RSFEC, yielding UFEC

RSFEC or RSFEC

RSFEC. In the example, UFEC module 24 handles termination on client andnetwork ports. EFEC module 26 is configured as a bidirectional wire.

FIG. 9 illustrates an example of a method in which FEC scheme X is EFECand FEC scheme Y is RSFEC, yielding EFEC

RSFEC. In the example, the network side stream may be terminated and/orgenerated in EFEC module 26. UFEC module 24 is configured as abidirectional wire.

FIG. 10 illustrates an example of a method in which FEC scheme X is UFECor RSFEC and FEC scheme Y is EFEC or RSFEC, yielding UFEC

RSFEC, RSFEC

RSFEC, UFEC

EFEC, or RSFEC

EFEC. In the example, the network side stream may be terminated and/orgenerated in UFEC module 24 and/or EFEC module 26.

FIGS. 11 and 12 illustrate examples of methods that may be used forconversion between OTU Optical Carrier 192 (OC192)/10 GigabitEthernet-wide area network (10GE-WAN) signals, that is, OTU

OC192/10GE-WAN. In certain embodiments, an OC192/10GE-WAN client sidesignal may be transported over a 10.709G OTU network side port. Overheadtermination may be supported for SM, PM, and TCM levels. Overheadprocessing may include processing of forward and/or backward defects.

FIG. 11 illustrates an example of a method in which FEC scheme X isUFEC, RSFEC, or no FEC (NO-FEC) In the example, UFEC module 24 handlesOTU termination on the network port. For a stream received from networkinterface 20, UFEC module 24 demaps the stream and operates in anasynchronous mode. UFEC module 24 provides reference and feedback clocksto controller 40 for use as inputs to the phase comparison logic for theasynchronous PLL (ASYNC-PLL). The demapped signal and its recoveredtiming may be passed to EFEC module 26 for transport overhead (TOH)processing and/or performance management and then sent to clientinterface 32.

For a stream received from client interface 32, the processing isreversed. UFEC module 24 may be configured for asynchronous orsynchronous mapping. UFEC module 24 may configured to insert events intothe stream for asynchronous mapping, but not for synchronous mapping.

FIG. 12 illustrates an example of a method in which FEC scheme X isEFEC. In the example, UFEC module 24 is configured as a bidirectionalwire. EFEC module 26 provides OxU2 support.

FIGS. 13 and 14 illustrate examples of methods that may be used forconversion between OTU Optical Carrier 192 (OC192) and 10 GigabitEthernet/10 Gigabit Fiber Channel (10GFC) Overclocked, that is, OTU

10GE/10GFC Overclocked.

FIG. 13 illustrates an example of a method in which FEC scheme X isUFEC, RSFEC, or NO-FEC. In the example, UFEC module 24 may be similar tothat of the OTU

OTU application, except that UFEC module 24 may source the OpticalChannel Data unit (ODU) 2 overhead toward the network and/or clientports.

Optical Channel Payload unit (OPU) 2 of the stream from networkinterface 20 and its associated overhead passes through UFEC module 24to/from EFEC module 26 over the interchip OTU. This may allow EFECmodule 26 to perform the bit synchronous mapping/demapping. The OPU2from EFEC module 26 is passed through UFEC module 24. UFEC module 24 mayoverwrite the path trace identifier (PTI).

FIG. 14 illustrates an example of a method in which FEC scheme X isEFEC. In the example, UFEC module 24 is configured as a bidirectionalwire, and EFEC module 26 terminates the network side OxU2.

FIGS. 15 and 16 illustrate examples of methods that may be used forconversion between OTU and Optical Carrier 192 (OC192) 10 GigabitEthernet Generic Framing Procedure-Frame Mode(GFP-F)/GFP-Semi-Transparent (GFP-ST), that is, OTU

10GE GFP-F/GFP-ST.

FIG. 15 illustrates an example of a method in which FEC scheme X isUFEC, RSFEC, or NO-FEC. In the example, UFEC module 24 may be similar tothat of the OTU

OTU application, except that UFEC module 24 may source ODU overheadtoward the network and/or client ports. OPU of the stream from networkinterface 20 and the associated overhead passes through UFEC module 24to/from EFEC module 26 over the interchip OTU, allowing EFEC module 26to perform the bit synchronous mapping/demapping. The OPU2 from EFECmodule 26 is passed through UFEC module 24. UFEC module 24 may overwritethe path trace identifier (PTI).

FIG. 16 illustrates an example of a method in which FEC scheme X isEFEC. UFEC module 24 is configured as a bidirectional wire, and EFECmodule 26 terminates the network side OxU2.

Modifications, additions, or omissions may be made to the systemsdisclosed herein without departing from the scope of the invention. Thecomponents of the systems may be integrated or separated. Moreover, theoperations of the systems may be performed by more, fewer, or othercomponents. Additionally, operations of the systems may be performedusing any suitable logic comprising software, hardware, and/or otherlogic. As used in this document, “each” refers to each member of a setor each member of a subset of a set.

Modifications, additions, or omissions may be made to the methodsdisclosed herein without departing from the scope of the invention. Themethods may include more, fewer, or other steps. Additionally, steps maybe performed in any suitable order.

Although this disclosure has been described in terms of certainembodiments, alterations and permutations of the embodiments will beapparent to those skilled in the art. Accordingly, the above descriptionof the embodiments does not constrain this disclosure. Other changes,substitutions, and alterations are possible without departing from thespirit and scope of this disclosure, as defined by the following claims.

1. A system comprising: a substrate; a plurality of forward errorcorrection (FEC) modules disposed outwardly from the substrate, theplurality of FEC modules comprising: a first FEC module configured toperform forward error correction according to a first FEC scheme; and asecond FEC module configured to perform forward error correctionaccording to a second FEC scheme; and a controller configured to:configure the first FEC module and the second FEC module to convert froman input FEC scheme to an output FEC scheme for a stream by identifyingthat the input FEC scheme is the first FEC scheme, identifying that theoutput FEC scheme is the second FEC scheme, and configuring the firstFEC module and the second FEC module to convert from the first FECscheme to the second FEC scheme.
 2. The system of claim 1: the first FECscheme comprising Ultra FEC; and the second FEC scheme comprisingEnhanced FEC.
 3. The system of claim 1: the first FEC module configuredto perform forward error correction according to a common FEC scheme;and the second FEC module configured to perform forward error correctionaccording to the common FEC scheme.
 4. The system of claim 1, thecontroller configured to configure the first FEC module and the secondFEC module by: identifying that the input FEC scheme is the first FECscheme; identifying that the output FEC scheme is the first FEC scheme;and configuring the first FEC module to perform forward error correctionaccording to the first FEC scheme.
 5. The system of claim 1, thecontroller configured to configure the first FEC module and the secondFEC module by: identifying that the input FEC scheme is the second FECscheme; identifying that the output FEC scheme is the second FEC scheme;and configuring the second FEC module to perform forward errorcorrection according to the second FEC scheme.
 6. The system of claim 1,the controller configured to: identify an input signal type of a streamand an output signal type of the stream; and configure a clocking systemto convert from the input signal type to the output signal type.
 7. Thesystem of claim 1, further comprising a plurality of clock synthesizers,each clock synthesizer configured to translate a recovered clock to areference clock for one or more of the plurality of FEC modules.
 8. Thesystem of claim 1, further comprising a clock selector configured toselect a reference clock for one or more of the plurality of FECmodules.
 9. The system of claim 1, further comprising an overheadprocessor configured to: generate a frame overhead for the stream.
 10. Amethod comprising: performing, by a first forward error correction (FEC)module of a plurality of FEC modules, forward error correction accordingto a first FEC scheme; performing, by a second FEC module of theplurality of FEC modules, forward error correction according to a secondFEC scheme, the FEC modules disposed outwardly from a substrate; andconfiguring, by a controller, the first FEC module and the second FECmodule to convert from an input FEC scheme to an output FEC scheme for astream by identifying that the input FEC scheme is the first FEC scheme,identifying that the output FEC scheme is the second FEC scheme, andconfiguring the first FEC module and the second FEC module to convertfrom the first FEC scheme to the second FEC scheme.
 11. The method ofclaim 10: the first FEC scheme comprising Ultra FEC; and the second FECscheme comprising Enhanced FEC.
 12. The method of claim 10: performing,by the first FEC module, forward error correction according to a commonFEC scheme; and performing, by the second FEC module, forward errorcorrection according to the common FEC scheme.
 13. The method of claim10, the configuring the first FEC module and the second FEC modulefurther comprising: identifying that the input FEC scheme is the firstFEC scheme; identifying that the output FEC scheme is the first FECscheme; and configuring the first FEC module to perform forward errorcorrection according to the first FEC scheme.
 14. The method of claim10, the configuring the first FEC module and the second FEC modulefurther comprising: identifying that the input FEC scheme is the secondFEC scheme; identifying that the output FEC scheme is the second FECscheme; and configuring the second FEC module to perform forward errorcorrection according to the second FEC scheme.
 15. The method of claim10, further comprising: identifying an input signal type of a stream andan output signal type of the stream; and configuring a clocking systemto convert from the input signal type to the output signal type.
 16. Themethod of claim 10, further comprising: translating a recovered clock toa reference clock for one or more of the plurality of FEC modules. 17.The method of claim 10, further comprising: selecting a reference clockfor one or more of the plurality of FEC modules.
 18. The method of claim10, further comprising: generating, by an overhead processor, a frameoverhead for the stream.